The field of invention relates generally to circuit design; and, more specifically, to the automatic generation of PLL related designs.
A Phase Lock Loop (PLL) is commonly used to generate one or more clock signals for a digital circuit. FIG. 1 shows a typical PLL design. In FIG. 1, the oscillator 101 is a voltage controlled oscillator (VCO) that produces an output signal having a frequency that is proportional to the voltage placed at its input 101a. The frequency of the oscillator 101 output signal is divided in the feedback loop by the divider 102. The divider 102 is typically a counter that triggers an edge at its output signal only after xe2x80x9cNxe2x80x9d edges are observed in the VCO 101 output signal. Thus, the divider 102 divides the frequency of the VCO 101 output signal by a factor of xe2x80x9cNxe2x80x9d.
The PLL is used to effectively multiply the frequency of a reference clock by the factor of xe2x80x9cNxe2x80x9d. That is, the PLL may be viewed as having an input that corresponds to a reference clock (Ref_Clock) and an output that corresponds to the VCO 101 output signal. The PLL settles to a stable operating point when the frequency of the VCO 101 output signal is Nfo where fo is the frequency of the reference clock signal.
Phase comparator 103 produces an output based upon the phase difference between the divider 102 output signal and the reference clock signal. In the particular approach shown in FIG. 1, a stream of pulses appear on the xe2x80x9cupnxe2x80x9d signal if the phase of the divider 102 output signal lags behind the reference clock. The width of the pulses within xe2x80x9cupnxe2x80x9d pulse stream are proportional to the amount of lag that exists. Similarly, a stream of pulses appear on the xe2x80x9cdownxe2x80x9d signal if the phase of the divider 102 output signal is ahead of (i.e., xe2x80x9cleadsxe2x80x9d) the reference clock. The width of the pulses within the xe2x80x9cdownxe2x80x9d pulse stream are proportional to the amount of lead that exists.
If a pulse stream appears on the xe2x80x9cupnxe2x80x9d signal, pulses of current are supplied by charge pump 104 to the loop filter 105. This raises the voltage at the VCO 101 input because loop filter 105 acts as an integrator. Raising the voltage at the VCO 101 input increases the frequency of the VCO 101 output signal. Similarly, if a pulse stream appears on the xe2x80x9cdownxe2x80x9d signal, pulses of current are pulled by charge pump 104 from the loop filter 105 which lowers the voltage at the VCO 101 input. Lowering the voltage at the VCO 101 input decreases the frequency of the VCO 101 output signal. Note that the PLL should also have adequate phase margin such that phase detector 103 does not confuse the proper output signaling (e.g., sending a xe2x80x9cdownxe2x80x9d signal when the divider 102 output signal actually lags the reference clock).
During an initial synchronization time, the voltage at the VCO 101 input approaches its proper value (i.e., the voltage corresponding to a VCO output frequency of Nfo) as a result of the charge pump""s activity. During this time, the charge pump usually supplies and/or pulls current to/from the loop filter 105 in accordance with the aforementioned pulse streams. Eventually, when the VCO 101 input voltage corresponds to a VCO output signal frequency of Nfo, the phase detector 103 does not recognize any error (because the divider output now has a frequency of fo) and the charge pump effectively stops pumping current to/from the charge pump 104. At this point, the PLL is stabilized and the voltage at the VCO 101 input remains substantially constant.
Since the dynamic activity of the charge pump 103 in relation to the design of the loop filter 105 determines the proper voltage at the VCO 101 input, the small signal transfer characteristics of the loop filter 105 are of noteworthy concern in PLL applications. Small signal loop filter 105 transfer characteristics as well as other PLL features (e.g., the design of the VCO 101, etc.) are commonly viewed as belonging to the xe2x80x9canalogxe2x80x9d domain of semiconductor chip circuit design. That is, a PLL emphasizes an analog as opposed to digital perspective.
Frequently, however, a semiconductor chip (as a whole) is designed substantially from the perspective of the xe2x80x9cdigitalxe2x80x9d domain and, as a result, it is common for semiconductor chip designers (i.e., individuals who design a semiconductor chip) to have skills that emphasize or are limited to the digital domain. As a result, semiconductor chip designers commonly experience difficulty while attempting to design a suitable PLL for their semiconductor chip because of a PLL""s emphasis on the analog perspective.
A method that automatically generates a design for an analog phase lock loop (PLL) core in response to a desired clock frequency.